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? 1 ? e00y05a11-ps sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. CXA3572r 48 pin lqfp (plastic) absolute maximum ratings (ta = 25c) ? supply voltage v cc 1 5.5 v v cc 215 v v dd 4.6 v analog input pin voltage vina1 (pins 18, 19, 20, 22, 23, 24 and 25) gnd ? 0.3 to v cc 1 + 0.3 v vina2 (pin 16) gnd ? 0.3 to v cc 2 + 0.3 v digital input pin voltage vind (pins 34 and 35) v ss ? 0.3 to +5.5 v common input pin voltage vinad (pins 31, 32 and 33) gnd, v ss ? 0.3 to +5.5 v operating temperature topr ?15 to +75 c storage temperature tstg ?55 to +150 c allowable power dissipation (ta 25c) p d 600 mw operating conditions supply voltage v cc 1 ? gnd1 2.7 to 3.6 v v cc 2 ? gnd2 11.0 to 14.0 v v dd ? v ss 2.7 to 3.6 v driver/timing generator for color lcd panels description the CXA3572r is an ic designed to drive the color lcd panel acx306/312. this ic greatly reduces the number of peripheral circuits and parts by incorporating a rgb driver and timing generator for video signals and a vco onto a single chip. this chip has a built-in serial interface circuit and electronic attenuators which allow various settings to be performed by microcomputer control, etc. features color lcd panel acx306/312 driver supports ntsc and pal systems supports y/color difference and rgb inputs supports osd input power saving function (clock stopped) various setting control using a serial interface circuit (asynchronous type) electronic attenuators (d/a converter) vco (no external oscillator circuit) lpf (fc variable) common and psig output circuits sharpness function 2-point correction circuit r, g, b signal delay time adjustment circuit sync separation circuit d/a output pin (0 to 3v, 8 level output) output polarity inversion circuit supports ac drive for lcd panel during no signal applications compact lcd monitors, etc.
? 2 ? CXA3572r block diagram sub- cont b at t at t serial i/f pll counter h. filter rpd sck sen sdat vd xclr pof hdo vdo rgt v dd hck1 hck2 hst v ss wide dwn v ss en vck vst v dd test phase comparator g/y r/r-y b/b-y hue color matrix picture f0 picture gain color hue v cc 1 gnd1 mode +3v da lpf trap user- bright user- bright sub- bright gamma1 gamma2 osd b dc det b out r dc det r out g dc det g out com osd g osd r osd b sig.c v cc 2 nc psig out psig dc det ref da out psig- bright s/h lpf trap contrast contrast r- bright b- bright psig- bright blim 1 2 blim filter r, g, b sync in sync sep com blk xclp frp sh1 sh2 sh3 sh4 xstby1 xstby2 +3v digital block 3v analog block 12v analog block 3v gnd2 +12v timing generator vco adj fine vco adj coarse ir rp ck +3v 0v 0v psig powersw lpf sw hd_ csync com sub- contrast sub- cont r frp at t dl dl ref da serial i/f dac clock generator 36 37 38 39 40 41 42 43 44 45 46 47 48 35 34 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 32 33 sync sel picture
? 3 ? CXA3572r pin description pin no. symbol en vck vst test gnd2 com b dc det b out r dc det r out g dc det g out v cc 2 psig out psig dc det sig.c nc osd b osd r osd g v cc 1 g/y r/r-y b/b-y sync in da out ref filter rpd gnd1 sen sck sdat vd xclr pof 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 i/o o o o ? ? o o o o o o o ? o o i ? i i i ? i i i i o o o o ? i i i i i o description en pulse output v clock pulse output v start pulse output test (leave this pin open.) analog 12.0v gnd common pad voltage output for lcd panel b signal dc voltage feedback circuit capacitor connection b signal output r signal dc voltage feedback circuit capacitor connection r signal output g signal dc voltage feedback circuit capacitor connection g signal output analog 12.0v power supply psig output psig signal dc voltage feedback circuit capacitor connection r, g, b and psig output dc voltage adjustment osd b input osd r input osd g input analog 3.0v power supply g/y signal input r/r-y signal input b/b-y signal input sync separation circuit input/sync signal input dac output level shifter circuit ref voltage output for lcd panel internal filter circuit f0 adjusting resistor connection phase comparator output analog 3.0v gnd serial load input serial clock input serial data input vertical sync signal input power-on reset capacitor connection (timing output block) lcd panel power supply on/off (leave this pin open when not using this function.) input pin for open status l
? 4 ? CXA3572r pin no. symbol v dd hdo vdo rgt v ss hck1 hck2 hst v dd wide dwn v ss 37 38 39 40 41 42 43 44 45 46 47 48 i/o ? o o o ? o o o ? o o ? description digital 3.0v power supply hdo pulse output vdo pulse output right/left inversion switching signal output digital 3.0v gnd h clock pulse 1 output h clock pulse 2 output h start pulse output digital 3.0v power supply wide pulse output up/down inversion switching signal output digital 3.0v gnd input pin for open status
? 5 ? CXA3572r analog block pin description pin no. symbol pin voltage equivalent circuit description analog 12.0v gnd. 100k gnd2 vcc2 5k 125k 6 5 gnd2 ? common voltage output. the output voltage is controlled by serial communication. 6 com ? gnd2 vcc2 10k 5k 4k 7 9 11 15 smoothing capacitor connection for the feedback circuit of r, g, b and psig output signal dc level control. connect a low-leakage capacitor. 7 9 11 15 b dc det r dc det g dc det psig dc det 3.0v r, g, b and psig signal outputs. the dc level is controlled to match the sig.c pin voltage. low output in power saving mode. 8 10 12 14 b out r out g out psig out ? 100k gnd2 vcc2 5k 500 10 10 8 10 12 14 analog 12.0v power supply. 13 v cc 2 12.0v 200k gnd2 vcc2 200k 10p 16 r, g, b and psig output dc voltage setting. connect a 0.01f capacitor between this pin and gnd1. when using a sig.c of other than vcc2/2, input the sig.c voltage from an external source. 16 sig.c v cc /2 no connection. 17 nc ?
? 6 ? CXA3572r pin no. symbol equivalent circuit description pin voltage osd pulse inputs. when one of these input pins exceeds the vth1 level, all of the outputs go to black limiter level; when an input pin exceeds the vth2 level, only the corresponding output goes to white limiter level. connect these pins to gnd when not used. 18 19 20 osd b osd r osd g vth1 = v cc 1 1/3 vth2 = v cc 1 2/3 gnd1 vcc1 20k 18 19 20 in y/color difference input mode, input the y signal to pin 22, the r-y signal to pin 23 and the b-y signal to pin 24. in rgb input mode, input the g signal to pin 22, the r signal to pin 23 and the b signal to pin 24. pedestal clamp these pins with external coupling capacitors. 22 23 24 g/y: 1.8v r/r-y, b/b-y, rgb: 1.8v y/color difference: 2.0v sync separation circuit input, or composite sync/horizontal sync signal input. during input to the sync separation circuit, input via a capacitor. 25 sync in 0.9v da output. outputs the serial data converted to dc voltage. the current driving capacity is 1.0ma (max.). ref output. the current driving capacity (sink) is 1.6ma (max.). 27 ref v cc 1/2 g/y r/r-y b/b-y 25 gnd1 vcc1 1k 10k 22 23 24 gnd1 vcc1 1k 26 da out ? 26 gnd1 vcc1 80k 15p 27 100k gnd1 vcc1 25k analog 3.0v power supply. 21 v cc 13.0v
? 7 ? CXA3572r pin no. symbol equivalent circuit description phase comparator output. 29 1.8v serial clock, serial load and serial data inputs for serial communication. 31 32 33 sen sck sdat ? rpd 29 gnd1 vcc1 1k 100k analog 3.0v gnd. 30 ? gnd1 31 32 33 gnd1 vcc1 20k ? 1 vss pin voltage connect a resistor between this pin and gnd1 to control the internal lpf and trap frequencies. connect a 43k ? resistor (tolerance 2%, temperature characteristics 200ppm or less). this pin is easily affected by external noise, so make the connection between the pin and external resistor, and between the gnd side of the external resistor and the gnd1 pin as close as possible. 28 filter 1.2v gnd1 vcc1 500 28
? 8 ? CXA3572r digital block pin description pin no. symbol equivalent circuit description digital block outputs. 1 2 3 36 38 39 40 42 43 44 46 47 en vck vst pof hdo vdo rgt hck1 hck2 hst wide dwn ? digital block system reset, and serial clock, serial load and serial data inputs for serial communication. 35 31 32 33 xclr sen sck sdat ? vss 1 2 3 36 38 39 40 42 43 44 46 47 vss 35 31 32 33 vertical sync signal input. 34 vd ? vss 34 digital 3.0v power supply. 37 45 v dd ? digital 3.0v gnd. 41 48 v ss ? 4 test ? pin voltage test. leave this pin open.
? 9 ? CXA3572r setting conditions for measuring electrical characteristics use the electrical characteristics measurement circuit on page 21 when measuring electrical characteristics. for measurement, the digital block must be initialized and power saving must be canceled by performing settings 1, 2 and 3 below. in addition, the serial data must be set to the initial settings shown in the table below. setting 1. system reset after turning on the power, activate the tg block system reset by setting xclr (pin 35) low. the serial bus is set to the default values. setting 2. horizontal afc adjustment in the condition without sync input, adjust so that the hdo pulse output frequency is ntsc: 15.734 0.1khz and pal: 15.625 0.1khz. setting 3. canceling power saving mode the power-on default is power saving mode, so clear (set all ? 1 ? ) serial data ps0 and sync gen. v dd t r t r > 10s xclr (pin 35) system reset
? 10 ? CXA3572r note: if there is the possibility that data may be set at other than the above-noted addresses, set these data to ? 0 ? . a7 lsb address msb lsb data 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 a6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 a5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 a4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 a3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 a2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 1 a1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 1 0 0 1 a0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 d7 d6 d5 d4 d3 d2 d1 d0 user-bright (10000000/lsb) sub-bright r (1000000/lsb) sub-bright b (1000000/lsb) contrast (10000000/lsb) sub-contrast r (1000000/lsb) sub-contrast b (1000000/lsb) -1 (0000000/lsb) -2 (0000000/lsb) psig-bright (1000000/lsb) com-dc (1000000/lsb) color (1000000/lsb) hue (1000000/lsb) vco fine (10000000/lsb) black-limiter (100000/lsb) 0 0 0 0 0 0 psigsw (0) 0 0 0 0 lpfsw (0) 0 0 slsyp (1) syst (0) 0 0 0 0 slexvd (1) slfl (0) slmbk (0) test2 (1) sldwn (0) slfr (0) ponf (1) slrgt (0) sl4096 (0) trap (0) test1 (0) slclp1 (0) input sel (0) slpof (0) slclp0 (0) sync sel (1) sync gen (1) slwd (0) slvdo (0) picture-gain (00000/lsb) mode (0) ps0 (1) slntpl (0) slhdo (0) picture-f0 (000/lsb) da (000/lsb) lpf (000/lsb) vco coarse (000/lsb) test3 (0, 0) h position (100000/lsb) hdo position (00000/lsb) v position (01000/lsb) s/h position (000/lsb) sb position (100/lsb) test4 (00000000/lsb) msb serial data initial settings
? 11 ? CXA3572r electrical characteristics ? dc characteristics analog block (ta = 25 c, v cc 1 = v dd = 3.0v, v cc 2 = 12.0v, see page 10 for the dac) item current consumption 1 (y/color difference input) current consumption 2 (y/color difference input) current consumption 1 (rgb input) current consumption 2 (rgb input) current consumption 1 (ps0 = 0) current consumption 2 (ps0 = 0) current consumption 1 (sync gen = 0) current consumption 2 (sync gen = 0) b dc det pin voltage r dc det pin voltage g dc det pin voltage psig dc det pin voltage sig.c pin voltage g/y pin voltage r/r-y pin voltage 1 r/r-y pin voltage 2 b/b-y pin voltage 1 b/b-y pin voltage 2 sync in pin voltage ref pin voltage (power saving mode) filter pin voltage osd r, g, b input voltage sig. c input voltage i1 i2 irgb1 irgb2 ips01 ips02 isg1 isg2 v7 v9 v11 v15 v16 v22 v23 v23 v24 v24 v25 v27 v28 vsig.c symbol measurement conditions measure the inflow current to pin 21. measure the inflow current to pin 13. measure the inflow current to pin 21. measure the inflow current to pin 13. measure the inflow current to pin 21. measure the inflow current to pin 13. measure the inflow current to pin 21. measure the inflow current to pin 13. during y/color difference input during rgb input during y/color difference input during rgb input during no input min. typ. max. unit 34 3.4 28 3.4 7 0.3 14 0.3 3.0 3.0 3.0 3.0 6.0 1.8 2.0 1.8 2.0 1.8 1.1 0.2 1.2 50 10 42 10 11 1.0 27 1.0 v cc 1 6.5 16 1.0 12 1.0 ? ? ? ? gnd 5.0 ma v
? 12 ? CXA3572r item y ? 1 sync (y on sync) ? 2 r-y b-y y ? 1 sync (y on sync) ? 2 r-y b-y r, g, b ? 1 sync (g on sync) ? 2 r, g, b ? 1 sync (g on sync) ? 2 symbol measurement conditions min. typ. max. unit 0.35 0.15 0.245 0.311 0.35 0.15 0.4 0.2 0.7 0.3 0.490 0.622 0.5 0.2 0.7 0.3 vp-p y/color difference mode y, r-y, b-y signal input level 1 y/color difference mode y, r-y, b-y signal input level 2 rgb mode r, g, b signal input level 1 rgb mode r, g, b signal input level 2 input sel = 0 ( ? 6db attenuate off) input sel = 1 ( ? 6db attenuate on) input sel = 0 ( ? 6db attenuate off) input sel = 1 ( ? 6db attenuate on) ? 1 y signal level (sync level is not included.) ? 2 sync level of y (g) on sync signal.
? 13 ? CXA3572r control signal block (sync signal, serial-serial signal, xclr, digital output) (ta = ? 15 to +75 c, v cc 1 = v dd = 2.7 to 3.6v) item high level input voltage low level input voltage high level input voltage low level input voltage high level input current low level input current high level input current low level input current high level input current low level input current high level output voltage low level output voltage high level output voltage low level output voltage v ih 1 v il 1 v ih 2 v il 2 | i ih 1 | | i il 1 | | i ih 2 | | i il 2 | | i ih 3 | | i il 3 | v oh 1 v ol 1 v oh 2 v ol 2 symbol measurement conditions v in = v dd v in = 0v v in = v dd v in = 0v v in = v dd v in = 0v i oh = ? 1.2ma i ol = 4.0ma i oh = ? 0.6ma i ol = 2.0ma min. typ. max. unit v cc 1 0.7 v dd (v cc 1) 0.7 20 20 150 1.0 1.0 1.0 0.3 0.3 v cc 1 ? 0.7 0 2.0 0 20 2.6 2.6 applicable pins v a v ? 1 ? 2 , ? 3 , ? 4 ? 1 , ? 2 ? 3 (pull-down) ? 4 ? 5 ? 6 ? 1 sync in (pin 25) ? 2 sen (pin 31), sck (pin 32), sdat (pin 33) ? 3 vd (pin 34) ? 4 xclr (pin 35) ? 5 hck1 (pin 42), hck2 (pin 43), hst (pin 44) ? 6 en (pin 1), vck (pin 2), vst (pin 3), pof (pin 36), hdo (pin 38), vdo (pin 39), rgt (pin 40), wide (pin 46), dwn (pin 47)
? 14 ? CXA3572r electrical characteristics ac characteristics unless otherwise specified, settings 1 and 2, the serial data initial settings, and the following setting conditions are required. ta = 25 c, v cc 1 = 3.0v, v cc 2 = 12v, gnd1 = gnd2 = 0v, v ss = 0v, sw8/10/12/14 = off, no video input, sg1 input to tp25 note: serial data values in the table are hex notation. maximum gain between input and output minimum gain between input and output inverted and non-inverted gain difference gain difference between r, g and b sub-contrast variable amount sub-bright variable amount r, g, b, psig and com output voltage in power saving mode black limiter variable amount g max g min ? g inv ? g rgb ? g sc 1 ? g sc 2 ? v sb 1 ? v sb 2 v pso v bl 1 v bl 2 input sg2 (0.2vp-p) to tp22 and measure the output amplitude at tp12. input sg2 (0.2vp-p) to tp22 and measure the output amplitude at tp12. input sg2 (0.2vp-p) to tp22 and measure the inverted output amplitude vinv and the non-inverted output amplitude vninv at tp12. ? ginv = 20 log (vninv/vinv) input sg2 (0.2vp-p) to tp22 (tp23, tp24), measure the non-inverted output amplitude at tp8, tp10 and tp12, and obtain the maximum and minimum difference between these values. set cont = 26h, input sg2 (0.2vp-p) to tp22, and assume the non-inverted output amplitude at tp8 and tp10 when sub-cont r, b = 40h, 00h and 7fh as v1, v2 and v3, respectively. ? gsc1 = 20 log (v3/v1) ? gsc2 = 20 log (v2/v1) set u-brt = 1ah and measure the non-inverted level at tp8 and tp10 relative to the non-inverted black level at tp12 when sub-brt r, b = 7fh and 00h. measure the r, g, b, psig and com output voltages in power saving mode. set u-brt = 00h, measure the non-inverted black limit level at tp12 when blk-lim = 00h and 3fh, and assume the difference from the output dc voltage as v bl 1 and v bl 2, respectively. 22 ? 3 ? ? ? 2.0 2.0 ? 1.4 1.4 ? 2.5 5.0 25 0 0.4 0.6 ? 1.0 4.0 ? 0.9 2.0 100 3.0 ? db db db db db v mv v cont ffh mode 00h cont 00h mode 00h cont 2fh mode 00h cont 2fh sub-cont 00h sub-cont 7fh sub-brt r, b 00h sub-brt r, b 7fh blk-lim 00h blk-lim 3fh item symbol serial data setting (hex) measurement conditions min. typ. max. unit 19 ? 6 ? ? ? 4 1.0 ? 2.0 0.9 ? ? 4.5
? 15 ? CXA3572r white limiter variable amount black level difference between r, g and b rgb and psig output dc voltage dc voltage difference between rgb and psig psig-brt variable amount user-brt variable amount level difference between psig-blk and blk-lim hue variable amount r hue variable amount b picture variable amount color variable amount v wl ? v b vc ? vc vpb1 vpb2 ? ub1 ? ub2 ? vbb ? hur1 ? hur2 ? hub1 ? hub2 gp1 gp2 gc1 gc2 set cont = ffh, input sg2 (0.2vp-p) to tp22, measure the non-inverted white limit level, and obtain the difference from the output dc voltage. measure the non-inverted black level at tp8, tp10 and tp12, and obtain the maximum and minimum difference between these values. measure the output dc level (average voltage) at tp8, tp10, tp12 and tp14. measure the output average voltage difference at tp8, tp10 and tp14 relative to the output average voltage at tp12. assume the psig output amplitude when psig-brt = 00h and 7fh as vpb1 and vpb2, respectively. measure the non-inverted black level at tp12 when u-brt = 00h and ffh and assume the difference from the average voltage as ? ub1 and ? ub2, respectively. set blk-lim = 00h and measure the difference between the inverted and non-inverted black level at tp12 and tp14. set u-brt = 80h, cont = 80h, color = 40h, input sg4 (56mvp-p) to tp23, input sg4 (100mvp-p) to tp24, and assume the amplitude at tp8 when hue = 80h, 00h and 3fh as vb1, vb2 and vb3. similarly, assume the amplitude at tp10 as vr1, vr2 and vr3. ? hur1 = 20 log (vr2/vr1) ? hur2 = 20 log (vr2/vr1) ? hub1 = 20 log (vb2/vb1) ? hub2 = 20 log (vb2/vb1) set cont = 80h, input sg3 to tp22, and measure the tp12 amplitude at f0 relative to the tp12 amplitude at 100khz when pic-g = 00h and 1fh, respectively. input sg4 (160mvp-p) to tp23 and tp24, and assume the output amplitude at tp8 and tp10 when color = 00h, 40h and 50h as v1, v2 and v3, respectively. gc1 = 20 log (v1/v2) gc2 = 20 log (v3/v2) 0.6 ? 6.0 ? 10.0 2.0 4.8 2.0 ? 3 ? 5 ? 5 3 0 12 ? ? 1.0 300 6.2 300 ? ? ? 2.5 300 ? ? 2 ? 2 ? 2.5 ? ? 20 ? v mv v mv vp-p v db db db psig-brt 00h psig-brt 7fh u-brt 00h u-brt ffh slwd 1 hue 00h hue 3fh hue 00h hue 3fh pic-g 00h pic-g 1fh color 00h color 50h item symbol serial data setting (hex) measurement conditions min. typ. max. unit 0.3 ? 5.8 ? 8.5 1.0 4.5 1.4 ? 1.5 ? ? 1.5 ? 2.5 9 ? 0.5 mv
? 16 ? CXA3572r matrix amplitude ratio lpf characteristics trap characteristics frequency response ref output voltage da adjustment range gain 1 adjustment variable range b-y/ r-y g-y/ r-y g-y/ b-y fc1 fc2 fo frgb vref vda1 vda2 ? 1 ? 2 v 1mn v 1mx assume the tp10 output when sg4 (0.1vp-p) is input to tp23 as rr, the tp8 amplitude when sg4 (0.1vp-p) is input to tp24 as bb, the tp10 amplitude when sg5 (0.1vp-p) is input to tp23 as rg, and the tp8 amplitude when sg5 (0.1vp-p) is input to tp24 as bg. b-y/r-y = rr/bb g-y/r-y = rg/rr g-y/b-y = bg/bb input sg3 to tp22 and measure the frequency which results in ? 3db relative to the tp12 amplitude at 100khz when lpf = 01h and 07h. set u-brt = 30h, cont = dfh, input sg7 (13.5mhz) to tp22, tp23 and tp24, and measure the amount by which each output is attenuated relative to sg7 (100khz). set sw8, sw10 and sw12 = on, input sg3 to tp22, tp23 and tp24, and measure the frequency which results in ? 3db relative to the tp8, tp10 and tp12 amplitude at 100khz. measure the ref pin output voltage at the output current 1.5ma sink. measure the da output voltage when da = 00h and 07h. input sg2 (0.35mvp-p) to tp22 and measure the amplitude at tp8, tp10 and tp12. assume the output amplitude when gamma1 = 7fh as v1, when gamma1 = 3fh as v2, and when gamma1 = gamma2 = 3fh as v3. ? 1 = 20 log (v1/v2) ? 2 = 20 log (v3/v2) input sg2 (0.35mvp-p) to tp22 and read the gain transition points of the non-inverted output at tp12 when 1 = 00h and 1 = 7fh from the ire level of the input signal. 1 = 00h: v 1mn 1 = 7fh: v 1mx 0.85 0.41 0.15 ? ? ? 5.5 1.3 ? 2.6 12 12 ? 100 1.00 0.51 0.19 1.5 5.2 ? 27 ? 1.5 ? ? 14 14 ? ? 1.15 0.61 0.23 ? ? ? 18 ? 1.7 0.3 ? 16 16 0 ? mhz db mhz v v db ire cont 80h color 40h lpf 01h mode 00h lpf 07h mode 00h mode 00h trap 1 mode 00h da 00h da 07h cont 41h cont 41h output current 1.0ma output current ? 1.0ma item symbol serial data setting (hex) measurement conditions min. typ. max. unit
? 17 ? CXA3572r 2 adjustment variable range common control range osd threshold value data setup time data hold time minimum pulse width output transition time cross-point time difference hck duty v 2mn v 2mx commin commx vth1 osd vth2 osd ts0 ts1 th0 th1 tw1l tw1h tw2 ? t dtyhc input sg2 (0.35mvp-p) to tp22 and read the gain transition points of the non-inverted output at tp12 when 2 = 00h and 2 = 7fh from the ire level of the input signal. 2 = 00h: v 2mn 2 = 7fh: v 2mx measure the com output dc voltage when com-dc = 00h and 7fh, and measure the difference from the com output dc voltage when com-dc = 40h. input sg4 to tp18, tp19 and tp20, gradually raise the high level from 0v, and assume the high level voltage at which the output level goes to blk-lim level as vth1osd, and the high level voltage at which the output goes to white-lim level as vth2osd. sen setup time, activated by the rising edge of sck. (see fig. 3.) sdat setup time, activated by the rising edge of sck. (see fig. 3.) sen hold time, activated by the rising edge of sck. (see fig. 3.) sdat hold time, activated by the rising edge of sck. (see fig. 3.) sck pulse width. (see fig. 3.) sck pulse width. (see fig. 3.) sen pulse width. (see fig. 3.) measure the transition time of each output. 90pf load: hst output pin 120pf load: hck1 and hck2 output pins (see fig. 1.) measure the transition time of each output. 50pf load: dwn, wide, vck, vst, test, en, vdo, hdo, pof and rgt output pins (see fig. 1.) measure hck1/hck2. 120pf load (see fig. 2.) measure the hck1/hck2 duty. 120pf load ? ? ? 1.0 1.0 1.0 2.0 ? ? ? ? ? ? ? ? 50 ire v v ns ns ns ns s ns ns ns % cont 41h com-dc 00h com-dc 7fh 100 ? ? 1.3 0.8 0.8 1.8 150 150 150 150 210 210 1 ? 48 ? 50 ? 0.8 1.3 1.2 2.2 ? ? ? ? ? ? ? ? 52 item symbol serial data setting (hex) measurement conditions min. typ. max. unit tthl ttlh tthl ttlh 30 30 40 40 ? ? ? ? ? ? ? ?
? 18 ? CXA3572r electrical characteristic measurement method diagrams fig. 1. output transition time measurement conditions fig. 2. cross-point time difference measurement conditions fig. 3. serial transfer block measurement conditions ttlh 90% 10% tthl 50% ? t ? t sdat d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 sck sen ts1 th1 tw1h tw1l th0 tw2 ts0 50% 50%
? 19 ? CXA3572r sg no. waveform sg1 sg4 sg2 sg3 sg5 1h 3.0vp-p horizontal sync signal (csync) 4.7s 1h amplitude variable horizontal sync signal 0.1vp-p 0.1vp-p 1h sine wave video signal; frequency and amplitude variable high level variable 0v horizontal sync signal 25s 10s 25s 10s 3v low level variable horizontal sync signal
? 20 ? CXA3572r sg no. waveform sg6 sg7 sg8 1h 50mvp-p horizontal sync signal (csync) 4.7s 0.1vp-p 1h sine wave video signal 1h 0.15vp-p horizontal sync signal (csync) 4.7ns
? 21 ? CXA3572r electrical characteristics measurement circuit ? resistance value tolerance: 2%, temperature coefficient: 200ppm/ c or less locate this resistor as close to the ic pin as possible to reduce the effects of external signals. tp44 tp43 tp42 tp38 tp39 tp40 tp27 tp26 tp25 tp29 tp36 tp22 tp23 tp24 tp16 tp6 0.1 0.1 0.1 350p sw12 tp12 350p sw10 tp10 350p sw8 tp8 en vck vst test gnd2 b/b-y r/r-y g/y vcc1 osd r osd g osd b nc sig.c psig dc det psig out v cc 2 v dd hdo vdo rgt vss1 hck1 hck2 hst v dd wide dwn vss2 pof xclr vd sdat sck sen gnd1 rpd filter ref da out sync in +12v 0.01 47 +3v 0.01 0.01 0.01 0.01 47 0.1 0.01 tp2 tp3 +3v 0.01 47 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 1 2 3 4 com b dc det b out r dc det r out g dc det g out tp1 6 7 8 9 11 12 13 14 15 16 17 18 19 20 21 22 23 24 a a a 60n sw14 tp14 tp18 tp19 tp20 5 10 tp33 tp32 tp31 tp47 tp46 1 0.1 43k 6800p 3.3 10k 10 10 10 10 ? 100k buffer
? 22 ? CXA3572r description of operation 1) rgb and y/color difference signal processing block signal processing is comprised of picture, hue, matrix, lpf/trap, contrast, osd, sample-and-hold, correction, bright, sub-bright, sub-contrast and output circuits. input signal mode switching the input mode (rgb input, y/color difference input) can be switched by the serial communication settings. (during internal sync separation signal input) during rgb input: the g signal is input to pins 22 and 25, the b signal to pin 24, and the r signal to pin 23. during y/color difference input: the y signal is input to pins 22 and 25, the b-y signal to pin 24, and the r-y signal to pin 23. (during external sync signal input) during rgb input: the g signal is input to pin 22, the b signal to pin 24, the r signal to pin 23, csync/hd to pin 25, and vd to pin 34. during y/color difference input: the y signal is input to pin 22, the b-y signal to pin 24, the r-y signal to pin 23, csync/hd to pin 25, and vd to pin 34. ntsc/pal switching the input system (ntsc/pal) can be switched by the serial communication settings. picture circuit this performs aperture correction for the y signal. the center frequency to be corrected and the correction amount are controlled by serial communication. hue circuit this is the hue adjustment circuit for the color difference signal. it is controlled by serial communication. matrix circuit this circuit converts y, r-y and b-y signals into rgb signals. lpf circuit this is the band limitation filter for the rgb signal. it is used to eliminate the noise component generated at the front end of this ic. the cut-off frequency can be controlled by serial communication. in addition, when not using the lpf, it can be turned off by serial communication. trap circuit this is used to eliminate the dsp clock and rgb decoder carrier leak generated at the front end of this ic. in addition, when not using the trap, it can be turned off by serial communication. contrast adjustment circuit this adjusts the amplitude to set the input rgb signal to the appropriate output level. osd this inputs the osd pulses. there are two input threshold values: vth1 (vcc1 1/3) and vth2 (vcc1 2/3). when an input exceeds vth1, the corresponding output falls to the level specified by black-limiter. when an input exceeds vth2, the corresponding output rises to the level specified by white-limiter. also, when one of the rgb inputs exceeds vth1, any signal outputs not exceeding vth1 also fall to the level specified by black-limiter.
? 23 ? CXA3572r sh1: r signal sh pulse sh2: g signal sh pulse sh3: b signal sh pulse sh4: rgb signal sh pulse shs1, 2, 3, 4, 5, 6: serial data settings the sample-and-hold circuit performs sample and hold by receiving the sh1 to sh4 pulses from the tg block. since lcd panels perform color coding using an rgb delta arrangement, each horizontal line must be compensated by 1.5 dots. this relationship is reversed during right/left inversion. this compensation and other timing is also generated by the digital block. the sample-and-hold timing changes according to the phase relationship with the hck pulse, so the timing should be set to the shs1 to shs6 position in accordance with the actual board. correction in order to support the characteristics of lcd panels, the i/o characteristics are as shown in fig. 1. the 1 gain transition point a voltage changes as shown in fig. 2 by adjusting the serial bus register 1, and the 2 gain transition point b voltage changes as shown in fig. 3 by adjusting 2. s/h1 s/h4 s/h2 s/h4 s/h3 sh3 sh4 sh2 sh1 s/h4 r g b r g b hck1 a a' b b' c' c rgt = h (normal) sh1 sh2 sh3 sh4 b through a c shs1 a' through c' b' shs2 a through c b shs3 c' through b' a' shs4 c through b a shs5 b' through a' c' shs6 rgt = l (right/left inversion) sh1 sh2 sh3 sh4 b a through c shs1 a' c' through b' shs2 a c through b shs3 c' b' through a' shs4 c b through a shs5 b' a' through c' shs6 sample-and-hold circuit this circuit performs time axis correction for the rgb output signals in order to support the rgb simultaneous sampling systems of lcd panels. fig. 1 fig. 2 fig. 3 output input b a output input b' b a' a output input b' b a
? 24 ? CXA3572r set by black-limiter black-limiter sig.c black-limiter black-limiter sig.c white-limiter white-limiter black-limiter set by black-limiter set by psig-bright rgb in 1h inverted signal (internal) black frame display signal (internal) psig out rgb out bright circuit this is used to adjust the black-black amplitude of polarity-inverted rgb output signals. it is not interlinked with the transition points. white balance adjustment circuit this is used to adjust the white balance. the black level is adjusted by sub-bright, and the black-white amplitude is adjusted by sub-contrast. output circuit rgb output (pins 8, 10, and 12) signals are inverted each horizontal line by the frp pulse (internal pulse) supplied from the tg block as shown in the figure below. feedback is applied so that the center voltage (sig.c) of the output signal matches the reference voltage (vcc2 + gnd2)/2 (or the voltage input to sig.c (pin 16)). in addition, the white level output is clipped at the limiter operation point that is set by the serial communication white-limiter, and the black level output is clipped at the limiter operation point that is set by the serial communication black-limiter. the output psig signal level is normally adjusted by psig-bright, but during black frame display the level is specified by the black-limiter level at some timings. in addition, the rgb output also simultaneously goes to black-limiter level output.
? 25 ? CXA3572r 2) common voltage generation circuit block the common voltage circuit generates and supplies the common pad voltage to the lcd panel. the voltage is offset by serial communication using the sig.c voltage as the reference and then output. 3) da out output circuit the da out output circuit outputs dc 3.0v at equal divisions. 4) ref output circuit the ref output circuit generates and supplies the panel level shifter circuit reference voltage to the lcd panel. 5) sync system internal sync separation circuit sync separation is performed from the signal input from sync in (pin 25). an external sync signal can also be input from the same pin (sync in) according to the serial communication setting. serial communication setting sync sel = 0: internal sync separation. sync sel = 1: external sync signal input. (the internal sync separation circuit is set to power saving mode.) input pin (pin 25) processing during internal sync separation: input through an external capacitor (0.1f) during external sync signal input: directly coupled, input level 3vp-p positive or negative polarity pll and afc circuits (vco setting method) a pll circuit can be comprised by connecting a pll circuit phase comparator and frequency division counter and a vco circuit and external lpf circuit. the pll error detection signal is generated using the phase comparison output of the entire bottom of the horizontal sync signal and the internal frequency division counter as the rpd output. rpd output is converted to dc error voltage with the lag-lead filter, and then it controls the internal vco circuit to stabilize the oscillation frequency. the internal clock oscillation frequency is set as follows by adjusting vco-coarse/fine. adjust the vco-coarse/fine settings so that the hdo pulse output frequency in the condition without sync input is ntsc: 15.734 0.1khz and pal: 15.625 0.1khz. 6) power saving circuit (ps circuit) a power saving system can be realized together with the lcd panel by independently controlling (serial communication) the operation of each output block. this system is also effective for improving picture quality during power-on/off. the serial data ps0 and sync gen must be set in order to use this ic. for details of the setting methods, see the ? description of serial control operation ? and ? power supply and power saving sequence ? items. min: 25mhz max: 30mhz 5mhz clock oscillation frequency vco-coarse: f0 coarse setting (7 steps) from 5 to 25mhz vco-fine: variable by approximately 4mhz using the f0 coarse setting made by vco-coarse as the reference vco-coarse setting (7 steps) vco-fine setting range (255 steps)
? 26 ? CXA3572r 7) power supply and power saving sequence power-on for the CXA3572r and the lcd panel should be performed in the following order. pof (pin 36) is output as the panel v dd control signal. the pof output can be switched by the serial communication setting, and the pof setting can be made regardless of the power saving setting. panel power supply configuration using pof output v dd (digital 3v block) v cc 1 (analog 3v block) v cc 2 (analog 12v block) a1 b1 c1 lcd v dd (lcd panel 12v) d1 e1 when power saving is set to on or off, video display is automatically turned on or off at the above timings. a2 b2 c2 e2 d2 power-off power-on 12 fields 4 fields normal video display display setting period (no video display) picture cancel period (no video display) normal operation ps0 1, slsg 1 power saving ps0 = 0, slsg = 0 power saving ps0 0, slsg 0 power saving setting (serial control) power saving set da out (pin 26) operation ? 1 power saving canceled CXA3572r acx306 pof v dd v c c 1 power supply 3v power supply v cc 2 v dd power-off a2 b2 c2 d2 e2 min. 0 0 0 ? 3 150 max. ? ? ? ? 300 ms ? 1 after the digital 3v v dd has completely risen and xclr (pin 35) is completely high level. ? 2 after the 3v v dd /v cc 1 has completely risen. power-on a1 b1 c1 d1 e1 min. 0 0 0 100 ? 2 0 max. ? ? ? ? 100 ms slpof pof (pin 36) output 0 1 low level high level (v dd ) ? 3 after the panel 12v v dd has completely fallen.
? 27 ? CXA3572r 8) tg block h-position this adjusts the horizontal display position. set this function so that the picture center matches the center of the lcd panel. v-position this adjusts the vertical display position. set this function so that the picture center matches the center of the lcd panel. right/left (rgt) and/or up/down (dwn) inversion the video display direction can be switched. the horizontal direction can be switched between right scan and left scan, and the vertical direction between down scan and up scan. set the display direction in accordance with the lcd panel mounting position. overscan display mode (slwd) displaying black in the up/down 6 lines and right/left 18 (19) dots of the display area generates an overscan area (black frame) in the display area. fine adjustment of the black frame display position is performed by sb-position. ac driving of lcd panels during no signal the output signal runs freely so that the lcd panel is ac driven even when there is no sync signal from the sync in (pin 25) and vd (pin 34) pins. 240 lines normal display black frame display display area black display 228 lines 6 lines 6 lines display area 490 dots 453 dots
? 28 ? CXA3572r description of serial control operation 1) system reset after turning on the power, activate the tg block system reset by setting xclr (pin 35) low. (see fig. ) the serial bus is set to the default values. serial transfer timing sdat a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 sck sen d: data a: address v dd t r t r > 10s xclr (pin 35) system reset 2) control method control data consists of 16 bits of data which is loaded one bit at a time at the rising edge of sck. this loading operation starts from the falling edge of sen and is completed at the next rising edge. digital block control data is established by the vertical sync signal, so if data is transferred multiple times for the same item, the data immediately before the vertical sync signal is valid. analog (electronic attenuator) block control data becomes valid each time the sen signal is input. in addition, if 16 bits or more of sck are not input while sen is low, the transferred data is not loaded to the inside of the ic and is ignored. if 16 bits or more of sck are input, the 16 bits of data before the rising edge of the sen pulse are valid data.
? 29 ? CXA3572r a7 lsb address msb lsb data 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 a6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 a5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 a4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 a3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 a2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 1 a1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 1 0 0 1 a0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 d7 d6 d5 d4 d3 d2 d1 d0 user-bright (10000000/lsb) sub-bright r (1000000/lsb) sub-bright b (1000000/lsb) contrast (10000000/lsb) sub-contrast r (1000000/lsb) sub-contrast b (1000000/lsb) -1 (0000000/lsb) -2 (0000000/lsb) psig-bright (1000000/lsb) com-dc (1000000/lsb) color (1000000/lsb) hue (1000000/lsb) vco fine (10000000/lsb) black-limiter (100000/lsb) (0) (0) (0) (0) (0) (0) psigsw (0) (0) (0) (0) (0) lpfsw (0) (0) (0) slsyp (0) syst (0) (0) (0) (0) (0) slexvd (0) slfl (0) slmbk (0) test2 (1) sldwn (0) slfr (0) ponf (0) slrgt (0) sl4096 (0) trap (0) test1 (0) slclp1 (0) input sel (0) slpof (0) slclp0 (0) sync sel (0) sync gen (0) slwd (0) slvdo (0) picture-gain (00000/lsb) mode (0) ps0 (0) slntpl (0) slhdo (0) picture-f0 (000/lsb) da (000/lsb) lpf (000/lsb) vco coarse (000/lsb) test3 (00) h position (100000/lsb) hdo position (00000/lsb) v position (01000/lsb) s/h position (000/lsb) sb position (100/lsb) test4 (00000000/lsb) msb note: if there is the possibility that data may be set at other than the above-noted addresses, set these data to ? 0 ? . 2) serial data map the serial data map is as follows. values inside parentheses are the default values.
? 30 ? CXA3572r 3) description of control data user-bright this adjusts the brightness of the rgb output signals. adjustment from lsb msb decreases the amplitude (black ? black). sub-bright r/b this adjusts the brightness of the r and b output signals using the g output signal as the reference. adjustment from lsb msb decreases the amplitude (black ? black). contrast this adjusts the contrast of the rgb output signals. adjustment from lsb msb increases the amplitude (black ? white). sub-contrast r/b this adjusts the contrast of the r and b output signals using the g output signal as the reference. adjustment from lsb msb increases the amplitude (black ? white). -1 this sets the black side point level of the rgb output signals. adjustment from msb lsb lowers the point. when not adjusting -1, set -1: 0000000 (lsb). set the -1 point to the black side (lower side) of the -2 point. -2 this sets the white side point level of the rgb output signals. adjustment from lsb msb lowers the point. when not adjusting -2, set -2: 0000000 (lsb). set the -2 point to the white side (upper side) of the -1 point. psig-bright this adjusts the brightness of the psig output signal. adjustment from lsb msb decreases the amplitude (peak to peak). psig-sw this switches the psig circuit on and off. d7 mode 0 1 psig off psig on com-dc this adjusts the common output voltage. adjustment from lsb msb increases the output voltage. color this adjusts the color gain during y/color difference input. adjustment from lsb msb increases the gain. hue this adjusts the phase during y/color difference input. adjustment from lsb msb advances the phase.
? 31 ? CXA3572r vco-fine this finely adjusts the vco oscillation center frequency. adjustment from lsb msb increases the frequency. perform this adjustment after adjusting vco-coarse. vco-coarse this roughly adjusts the vco oscillation center frequency. adjustment from lsb msb increases the frequency. adjust with vco-fine set to 10000000 (lsb). black-limiter this adjusts the black side limiter level of the rgb output signals. adjustment from lsb msb lowers the limiter level. picture-gain this adjusts the picture gain during y/color difference input. adjustment from lsb msb raises the gain. when not using the picture function, set picture-gain: 00000 (lsb). picture-f0 this sets the picture center frequency (f0) during y/color difference input. see the ac characteristics for the output level. d2 center frequency (f0) typ. 0 0 0 0 1 1 1 1 d1 0 0 1 1 0 0 1 1 d0 0 1 0 1 0 1 0 1 1.0mhz 1.3mhz 1.6mhz 1.9mhz 2.2mhz 2.5mhz 2.8mhz 3.1mhz lpf this switches the frequency response of the low-pass filter. set the fc/ ? 3db frequency relative to the amplitude 100khz reference. see the ac characteristics for the output level. d6 fc (rgb input/no load/typ.) 0 0 0 0 1 1 1 1 d5 0 0 1 1 0 0 1 1 d4 0 1 0 1 0 1 0 1 ? 1.5mhz 2.1mhz 2.7mhz 3.5mhz 4.1mhz 4.6mhz 5.2mhz
? 32 ? CXA3572r trap this switches the trap circuit on and off. da this adjusts the da output voltage. adjustment from lsb msb raises the output voltage level. input-sel set this according to the input signal level. sync sel this switches between internal sync separation and external sync signal input. mode this switches the input signal. lpf-sw this switches the lpf circuit on and off. ps0 (default: 0) this performs the power saving setting. be sure to use this setting as described in ? power supply and power saving sequence ? . the power-on default for this ic is power saving mode, so the settings should be canceled by serial communication after power-on. the lcd panel power supply must be turned off in power saving mode. d0 input signal 0 1 rgb input y/color difference input d7 mode 0 1 lpf off lpf on d3 mode 0 1 trap off trap on d2 mode 0 1 normal input internally attenuated by ? 6db input signal level 0.35vp-p or less, 0.5vp-p or less with sync 0.35vp-p or more, 0.5vp-p or more with sync d1 mode 0 1 internal sync separation external sync signal input (internal sync separation circuit power saving) input connection method input via a coupling capacitor input level 3vp-p positive or negative polarity ps0 mode 0 1 power saving normal operation
? 33 ? CXA3572r test2 mode 0 1 test mode normal operation test2 (default: 0) this is the test mode. set to ? 1 ? . ponf mode 0 1 12 fields 4 fields ponf (default: 0) this switches the time until the picture is displayed after power saving is canceled. test0 mode 0 1 normal operation test mode test1 (default: 0) this is the test mode. set to ? 0 ? . slpof mode 0 1 pof = low output pof = high output slpof (default: 0) this sets the pof (pin 36) output. the pof output setting can be made regardless of the power saving mode. sync gen mode 0 1 sync generator mode normal operation sync gen (default: 0) this sets the sync generator mode. in sync generator mode, only the hdo and vdo pulses are output normally, and all other pulses are low. the lcd panel power supply must be turned off in sync generator mode. normally set to ? 1 ? . slntpl (default: 0) this switches between ntsc and pal mode. slntpl mode 0 1 ntsc pa l
? 34 ? CXA3572r slsyp (default: 0) this switches the input sync signal polarity. when performing sync separation with the internal sync separation circuit from yonsync or gonsync, set this to ? 0 ? . slsyp hd/csync, vsync polarity 0 1 positive polarity negative polarity slexvd (default: 0) this sets the external vd input. the external vd signal is input via vd (pin 34). when using internal vertical sync separation, vertical sync separation is performed using the csync input from sync in (pin 25). slexvd setting 0 1 internal vertical sync separation external vsync input sldwn (default: 0) this switches between normal and up/down inverted display. sldwn setting 0 1 normal display (down scan) up/down inverted display (up scan) slrgt (default: 0) this switches between normal and right/left inverted display. slrgt setting 0 1 normal display (right scan) right/left inverted display (left scan) test3 (default: 0, 0) this is the test mode. set to ? 0, 0 ? . test3 mode 0, 0 0, 1 1, 0 1, 1 normal operation test mode slwd (default: 0) this sets the up/down and/or right/left black frame display. slwd display 0 1 100% viewing field display black frame display (95% display)
? 35 ? CXA3572r slhdo hdo polarity 0 1 positive polarity negative polarity slvdo vdo polarity 0 1 positive polarity negative polarity sl4096 polarity inversion cycle 0 1 1h inversion 1h inversion + 4096-field inversion slfr polarity inversion cycle 0 1 1h inversion 1-field inversion slhdo (default: 0) this switches the hdo pulse output polarity. slvdo (default: 0) this switches the vdo pulse output polarity. slclp0, slclp1 (default: 0, 0) these switch the clamp position. sl4096 (default: 0) this function inverts the r, g, b and psig output signal polarities every 4096 fields. this further inverts the output polarities that are inverted every 1h for 4096 fields. slfr (default: 0) this function inverts the r, g, b and psig output signal polarities every field. normally set to 1h inversion. slclp1 position 0 0 1 1 a: back porch position (during internal sync separation) b: sync position (during internal sync separation) c: back porch position (during external sync signal input) d: sync position (during external sync signal input) slclp0 0 1 0 1 hsync xclp 01: b 00: a 10: c 11: d 1.3s 1.0s 2.0s 2.9s 2.0s 2.0s 2.0s 3.6s
? 36 ? CXA3572r h position (default: 100000/lsb) these set the horizontal display position. the hst pulse position is adjusted using the horizontal sync signal as the reference. adjustment is possible in 1 bit = 1fh increments. hdo position (default: 00000/lsb) these set the hdo pulse output position. the hdo pulse output position is adjusted using the horizontal sync signal as the reference. adjustment is possible in 1 bit = 4fh increments. slmbk decimation cycle 0 1 1/6, 1/6 decimation 1/6, 1/8 decimation slmbk (default: 0) this sets the decimation cycle in pal mode. syst mode 0 1 normal operation forced free-running syst (default: 0) this invalidates the input horizontal sync (csync, hd) and forcibly sets the free-running status. slfl polarity inversion cycle 0 1 polarity inversion polarity inversion stopped slfl (default: 0) this function is used to stop r, g, b and psig output signal polarity inversion. hsync hst hp: 100000 (lsb) default hp: 000000 (lsb) hp: 111111 (lsb) 30 steps (fh) 31 steps (fh) hsync hdo hp: 00000 (lsb) default hp: 11111 (lsb) 31 steps (124fh)
? 37 ? CXA3572r v position (default: 01000/lsb) these set the vertical display position. the vst pulse position is adjusted using the input vertical sync signal as the reference. adjustment is possible in 1 bit = 1h (1 line) increments. test4 (default: 00000000/lsb) this is the test mode. set to 00000000/lsb (8 bits). sb position (default: 100/lsb) in overscan display mode, fine adjustment of the right/left overscan area (black frame) position is possible in 1 bit = 1fh increments. hst (blk) sbp: 000 (lsb) sbp: 100 (lsb) sbp: 111 (lsb) 4 steps (4fh) 3 steps (3fh) 4 steps (4fh) 3 steps (3fh) vertical sync signal vst vp: 01000 (lsb) default vp: 00000 (lsb) vp: 11111 (lsb) 8 steps (8h) 23 steps (23h) d7 sample-and-hold position 0 0 0 0 1 1 1 1 d6 0 0 1 1 0 0 1 1 d5 0 1 0 1 0 1 0 1 shs1 shs2 shs3 shs4 shs5 shs6 through (sample-and-hold off) through (sample-and-hold off) s/h position (default: 000/lsb) these set the sample-and-hold pulse output phase.
? 38 ? CXA3572r application circuit ? 1 resistance value tolerance: 2%, temperature coefficient: 200ppm/ c or less ? 2 when using a signal center voltage other than vcc2/2, input an external signal center voltage. external hd input (0 to 3v) external vd input serial data input to lcd panel g/y r/r-y b/b-y 0.68 33 0.68 0.68 10 10 10 10 en vck vst test gnd2 b/b-y r/r-y g/y vcc1 osd r osd g osd b nc sig.c psig dc det psig out v cc 2 v dd hdo vdo rgt vss1 hck1 hck2 hst v dd wide dwn vss2 pof xclr vd sdat sck sen gnd1 rpd filter ref da out sync in +12v (analog) to lcd panel +3v (analog) 33 0.1 buffer 33 0.1 0.01 0.68 10 0.1 0.1 0.1 0.1 100k 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 1 2 3 4 com b dc det b out r dc det r out g dc det g out 6 7 8 9 11 12 13 14 15 16 17 18 19 20 21 22 23 24 5 10 0.1 0.01 6800p 3.3 43k 10k ? 1 ? 2 33 0.1 +3v (digital) to lcd panel to lcd panel to lcd panel +12v 22k psig buffer circuit 22k out in (analog) 10 10 application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same .
? 39 ? CXA3572r notes on operation (1) this ic contains digital circuits, so the set board pattern must be designed in consideration of undesired radiation, interference to analog circuits, etc. care should also be taken for the following items when designing the pattern. the digital and analog ic power supplies should be separated, but the gnd and v ss should not be separated and should use a plain gnd (v ss ) pattern in order to reduce impedance as much as possible. the power supplies should also use a plain pattern. use ceramic capacitors for the by-pass capacitors between the power supplies and gnd, and connect these capacitors as close to the pins as possible. the resistor connected to pin 28 should be connected as close to the pin as possible, and the wiring from the pin to gnd should be as short as possible. also, do not pass other signal lines close to this pin or the connected resistor. (2) the g/y (pin 22), r/r-y (pin 23), b/b-y (pin 24) and sync in (pin 25) pin input signals are clamped at the inputs using the capacitors connected to each pin, so these signals should be input at sufficiently low impedance. (input at an impedance of 1k ? (max.) or less.) (3) the smoothing capacitor of the dc level control feedback circuit in the capacitor block connected to the rgb output pins should have a leak current with a small absolute value and variance. also, when using the pulse elimination (pal display) function, the picture quality should be thoroughly evaluated before deciding the capacitance value of the capacitor. (4) a thorough study of whether the capacitor connected to the com output pin satisfies the lcd panel specifications should be made before deciding the capacitance value. (5) if this ic is used in connection with a circuit other than an lcd, it may cause that circuit to malfunction depending on the order in which power is supplied to the circuits. thoroughly study the consequences of using this ic with other circuits before deciding on its use. (6) since this ic utilizes a c-mos structure, it may latch up due to excessive noise or power surge greater than the maximum rating of the i/o pins, or due to interface with the power supply of another circuit, or due to the order in which power is supplied to circuits. be sure to take measures against the possibility of latch up. (7) be sure to observe the power supply and power saving sequence specifications specified for this ic. (8) do not apply a voltage higher than v dd or lower than v ss to i/o pins. (9) do not use this ic under operating conditions other than those given. (10) absolute maximum rating values should not be exceeded even momentarily. exceeding ratings may damage the device, leading to eventual breakdown. (11) this ic has a mos structure which is easily damaged by static electricity, so thorough measures should be taken to prevent electrostatic discharge. (12) always connect the v ss , gnd1 and gnd2 pins to the lowest potential applied to this ic; do not leave these pins open. the voltages applied to the power supply pins should be as follows. v ss = gnd1 = gnd2 v dd = v cc 1 v cc 2. (13) be sure to connect the damping resistor of 10 ? to rout, gout, bout, psigout and com output.
? 40 ? CXA3572r sony corporation package outline unit: mm sony code eiaj code jedec code package material lead treatment lead material package mass epoxy resin copper alloy package structure 48pin lqfp (plastic) 9.0 0.2 ? 7.0 0.1 1 12 13 24 25 36 37 48 (0.22) 0.18 ? 0.03 + 0.08 0.2g lqfp-48p-l01 p-lqfp48-7x7-0.5 (8.0) 0.5 0.2 0.127 ? 0.02 + 0.05 a 1.5 ? 0.1 + 0.2 0.1 palladium plating note: dimension ? ? ? does not include mold protrusion. 0.1 0.1 0.5 0.2 0? to 10? detail a 0.13 m 0.5 s s b detail b : palladium 0.127 0.04 0.18 0.03

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